The PWM IP is a configurable and efficient way for generating precise pulse width modulation signals. Featuring dynamic duty cycle adjustment, flexible prescalers, and interrupt-driven efficiency, it ensures optimal performance across various powersensitive applications
sPort | Width | Direction | Description |
---|---|---|---|
clk | 1 | Input | Global Input Signal |
rst_n | 1 | Input | Active low global signal |
feed | 1 | Input | Signal from processor to reset the WDT counter |
scan_mode | 1 | Input | Scan mode selection signal (DFT Signal) |
scan_en | 1 | Input | Scan enable signal (DFT Signal) |
nmi | 1 | Output | Interrupt Signal for Timeout Value 1 |
reset | 1 | Output | Reset Signal for the processor |
int_o | 1 | Output | Interrupt Signal for Timeout Value 2 |
Generic Bus Interface | 98 | Input/Output | Generic Bus Interface Signals. More details in the design document |
sPort | Width | Direction | Description |
---|---|---|---|
clk | 1 | Input | Global Input Signal |
rst_n | 1 | Input | Active low global signal |
feed | 1 | Input | Signal from processor to reset the WDT counter |
scan_ mode |
1 | Input | Scan mode selection signal (DFT Signal) |
scan_en | 1 | Input | Scan enable signal (DFT Signal) |
nmi | 1 | Output | Interrupt Signal for Timeout Value 1 |
reset | 1 | Output | Reset Signal for the processor |
int_o | 1 | Output | Interrupt Signal for Timeout Value 2 |
Generic Bus Interface | 98 | Input/ Output |
Generic Bus Interface Signals. More details in the design document |